The subject invention generally relates to ink jet printing, and more particularly to thin film ink jet printheads having integrated dynamic memory circuitry within each firing cell.
The art of ink jet printing is relatively well developed. Commercial products such as computer printers, graphics plotters, and facsimile machines have been implemented with ink jet technology for producing printed media. The contributions of Hewlett-Packard Company to ink jet technology are described, for example, in various articles in the Hewlett-Packard Journal, Vol. 36, No. 5 (May 1985); Vol. 39, No. 5 (October 1988); Vol. 43, No. 4 (August 1992); Vol. 43, No. 6 (December 1992); and Vol. 45, No. 1 (February 1994); all incorporated herein by reference.
Generally, an ink jet image is formed pursuant to precise placement on a print medium of ink drops emitted by an ink drop generating device known as an ink jet printhead. Typically, an ink jet printhead is supported on a movable carriage that traverses over the surface of the print medium and is controlled to eject drops of ink at appropriate times pursuant to command of a microcomputer or other controller, wherein the timing of the application of the ink drops is intended to correspond to a pattern of pixels of the image being printed. An ink jet printhead is commonly mounted on an ink jet print cartridge that, for example, can include an integral ink reservoir.
A typical Hewlett-Packard ink jet printhead includes an array of precisely formed nozzles in an orifice or nozzle plate that is attached to an ink barrier layer which in turn is attached to a thin film substructure that implements ink firing heater resistors and apparatus for enabling the resistors. The ink barrier layer defines ink channels including ink chambers disposed over associated ink firing resistors, and the nozzles in the orifice plate are aligned with associated ink chambers. Ink drop generator regions are formed by the ink chambers and portions of the thin film substructure and orifice plate that are adjacent the ink chambers.
The thin film substructure is typically comprised of a substrate such as silicon on which are formed various thin film layers that form thin film ink firing heater resistors, circuitry for enabling the transfer of ink firing energy to the heater resistors, and also conductive traces to interface pads that are provided for external electrical interconnections to the printhead.
The ink barrier layer is typically a polymer material that is laminated as a dry film to the thin film substructure, and is designed to be photo-definable and both UV and thermally curable.
An example of the physical arrangement of the orifice plate, ink barrier layer, and thin film substructure is illustrated at page 44 of the Hewlett-Packard Journal of February 1994, cited above. Further examples of ink jet printheads are set forth in commonly assigned U.S. Pat. No. 4,719,477 and U.S. Pat. No. 5,317,346, both of which are incorporated herein by reference.
There is a trend in thermal ink jet technology to increase the number of nozzles constructed on a single printhead as well as to increase the firing rate of those nozzles. As the number of nozzles increase, the number of external electrical interconnections to the printhead increases dramatically unless some form of multiplexing is implemented wherein some of the interconnections are shared by the ink firing resistors on a time division basis so as to reduce the number of interconnections to the printhead.
A known multiplexing scheme involves the provision of a gating transistor for each ink firing resistor, whereby current to an ink firing resistor flows only when its associated gating transistor is selected (i.e., rendered conductive). By arranging each resistor and associated transistor in a matrix of rows and columns, the total number of external electrical interconnections is substantially reduced. Printheads employing this multiplexing scheme have been made using low cost NMOS integrated circuit processing.
Optimally, the matrix of rows and columns would be square (i.e., the number of rows equals the number of columns) in order to have a minimum number of external interconnections. However, the matrix is typically implemented as a rectangular matrix as result of system requirements such as the maximum rate at which each resistor can be successively energized (firing rate), the time between successive firings of different resistors (firing cycle), and the number of resistors that can be fired in a firing cycle. With a rectangular matrix, the number of external interconnections is considerably greater than the square optimum.
Another known interconnect reduction scheme incorporates logic circuitry and static memory elements on the printhead substrate within each firing cell and on the periphery of the array of firing cells. In this scheme, while one row or column of heater resistors is firing, static memory elements receive and store firing data for the next row or column of resistors to be energized. An example of a printhead that incorporates logic circuitry and static memory elements on the printhead substrate for multiplexing is the Hewlett-Packard C4820A 524-nozzle printhead used by the Hewlett-Packard DesignJet 1050C large format printer. A consideration with incorporating logic circuitry and static memory elements on a printhead substrate is that this typically requires a more complex integrated circuit process, such as CMOS, which increases cost as compared to NMOS integrated circuit processing since CMOS processing typically requires more mask levels and processing steps than NMOS processing. Moreover, incorporating logic circuitry on the periphery of the firing array increases the complexity of the layout process, which increases overall development time for new or modified printheads.
For typical non-printhead integrated circuits, the cost of an individual die can be reduced over time by implementing the same functions in a more complex (and thereby more expensive) integrated circuit process that produces smaller die sizes with the same functionality. A smaller die results in more die per fixed size wafer and thus an overall lower cost per die, even though wafer cost increases as a result the increased process complexity.
Ink jet printheads made with integrated circuit processes cannot follow the typical integrated circuit cost trend of smaller die and therefore lower cost, since the size of an integrated circuit ink jet printhead is fixed in one dimension by the desired print swath height, and in a second dimension by the desired number of independent fluidic channels and their physical spacing requirements. The increased cost of printheads fabricated with integrated circuit processes of greater complexity cannot be offset by reductions in the size of the printhead without losing printhead functionality such as a loss in printing throughput or a loss in the number of colors on each printhead.
There is therefore a need for an integrated circuit ink jet printhead having reduced external interconnections and which can be made using low cost NMOS integrated circuit processing.